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    • 专利摘要:
    A pixel structure has an epitaxial layer (1) of a first conductivity type. A photosensitive element has a first region (4) of a second conductivity type and a second region (3) of a first conductivity type, between an epitaxial layer [1) and the first region (4). A charge storage node (02) is designed to store charge 10, or form part of a charge storage element. A third region (2) of the second conductivity type is located between the charge storage node and the epitaxial layer. The pixel structure includes a conversion element (13) to convert charge to a voltage signal and an output circuit (21, 22) to output the voltage signal.
    公开号:BE1022430B1
    申请号:E2014/0098
    申请日:2014-02-14
    公开日:2016-03-30
    发明作者:Guy Meynants；Wichelen Koen Van
    申请人:Cmosis Bvba；
    IPC主号:
    专利说明:

    A pixel structure
    Application domain
    This invention relates to pixel structures and matrices of pixel structures used in applications such as image sensors.
    Background
    An image sensor consists of a matrix of pixel structures. The matrix can be used with a rolling shutter or with a global shutter. With a rolling shutter, the exposure time is slightly shifted for each row of the pixel matrix. This leads to distortions of the scene. With a global shutter, all pixels are exposed together (synchronously). A global shutter is needed to record fast-moving objects or when the camera itself is moving. This is typically required in high speed applications or in machine vision. A global shutter requires a memory element in the pixel to save the recorded image during the readout time. That stored pixel value is then read out row-by-row while the next image is being recorded.
    In some known global shutter pixel configurations, charges are stored in a potential well, in the charge domain. This charge storage node may inadvertently collect additional photoelectrons during a charge storage period. These additional photoelectrons are intended to be collected by the photodiode instead of by the charge storage node, but some charges will diffuse and be collected by the charge storage node instead of by the photodiode. This results in a parasitic light sensitivity of the storage nodes.
    Figure 1 shows a global shutter pixel with in-pixel charge storage below a storage port 02. A cross-section is shown of the photodiode, charge transfer gates 0, 02 and 03, the floating diffusion fd, the reset transistor RST and the anti-overload charge drain AB. The source follower and selection transistor are only shown at circuit level. The photodiode is a pinned photodiode where the surface is pinned to ground potential by a p + surface implantation layer. This p + implantation layer is connected to the ground potential (not shown in the drawing). The diode itself is formed by an n-type implantation under this pinning implantation, and thus forms a junction with the p + surface implantation and the p-epitaxial layer. Charges are transferred from the photodiode to the storage node 02 via the transfer port 11 at the end of the exposure time. At readout, the floating diffusion fd is reset by RST, and then the charge is transferred from 02 to fd by pulsing the 02 and 03 gates.
    After the signal is sampled under 02, and while the signal is stored under 02, the following image is recorded. Photo-generated electrons are created in the substrate. The electrons generated in the β-epitaxial layer must be collected by the photodiode. Some of these charges are generated within the depletion region of the photodiode and are collected immediately. Other charges are generated outside this depletion region and must diffuse until they reach an electric field formed by the photodiode or another junction or gate in the pixel structure. Two such electrons are shown. An electron diffuses and is collected by the photodiode. However, another electron diffuses until it is collected through the storage gate 02, which is set to a high potential during storage. There is no additional barrier that prevents this electron from diffusing into this gate. A significant portion of the electrons is collected by this storage node. A light screen 11 can be used to shield the storage node. However, this is only partly sufficient because the electrons move randomly.
    Figure 2 shows a known improvement intended to prevent charge from diffusing to the storage nodes. This improvement is described, for example, in US patent # 6,225,670, and provides for a higher p dose under the storage node. The difference in concentration between the p-well layer and the p-epitaxial layer is sufficient to create a small potential barrier. The potential barrier is given by:
    where Na and Na + are the acceptor concentrations for the p and p + regions in the pixel and kT / q is the thermal stress (k = Boltzmann constant, T = absolute temperature, q = elemental charge). Typical concentrations for the p-well are 1E17 / cm 3, while typical concentrations of the epitaxial layer are 5E14 / cm 3. This forms a barrier of 134 mV at room temperature. Figure 3 shows the electrostatic potential along the sections A-A ', BB' and CC 'in Figures 1 and 2. Another example of the use of a doping profile to shield unrelated junctions in the charge collection pixel is shown in US patent application US 2007 / 0109437A1.
    The present invention seeks a way to improve the efficiency of the shutter by reducing the parasitic light sensitivity of the storage nodes in the pixel structure.
    Summary
    An aspect of the invention relates to a pixel structure comprising: an epitaxial layer of a first conductivity type; a photosensitive element comprising a first region of a second conductivity type and a second region of the first conductivity type positioned between the epitaxial layer and the first region; a charge storage node which is configured to store charge collected by the photosensitive element, or to form part of a charge storage element; a third region of the second conductivity type positioned between the charge storage element and the epitaxial layer; a charge-to-voltage conversion element for converting charge from the charge storage element to a voltage signal; and, an output circuit for selectively outputting the voltage signal from the pixel.
    Advantageously, the first conductivity type is n-type and the second conductivity type is p-type.
    Advantageously, the photosensitive element is a pinned photodiode. Advantageously, the doping level of the third region is higher than the doping level of the epitaxial layer. The doping level of the third region can be higher than the doping level of the epitaxial layer by a factor of at least 100, or by a factor between 200 and 1000.
    Advantageously, the doping level of the second region is greater than the doping level of the epitaxial layer. The doping level of the second region can be higher than the doping level of the epitaxial layer by a factor of at least a hundred, or by a factor between 100 and 2000.
    Advantageously, the charge storage node comprises one of the following elements: a floating diffusion, a transfer port, a capacitance plate, a pinned diode.
    Advantageously, the charge conversion element is an area of the first conductivity type within the third area.
    Advantageously, the charge storage node and the charge conversion element is an area of the first conductivity type within the third area.
    Advantageously, the charge storage element is positioned between the photosensitive element and the charge-to-voltage conversion element. This is useful for pixel structures where there is in-pixel storage in the load domain.
    Advantageously, the pixel structure further comprises on its at least one of: a transfer port positioned between the photosensitive element and the charge storage node; and a transfer port positioned between the charge storage node and the charge-to-voltage conversion element.
    Advantageously, the charge storage node is positioned between the charge-to-voltage conversion element and the output circuit. The charge storage node may form part of a charge storage element, and may, for example, be a junction of a switch connected to a capacitance, or a gate-to-channel capacitance of a transistor serving as a charge storage element. In this case, the charge storage node can also benefit from shielding, although it is not the main charge storage element.
    Advantageously, the third region extends into the first region and the second region of the photosensitive element.
    Advantageously, the pixel structure further comprises insulating layers of the second conductivity type adjacent to an edge of the pixel structure to prevent lateral diffusion of charges, the insulating regions being located in the epitaxial layer. The insulating regions may extend between the third region and an underside of the epitaxial layer.
    Advantageously, the pixel structure further comprises an anti-over exposure port positioned between the photosensitive element and a power supply connection.
    Advantageously, the pixel structure further comprises one of: a substrate of a second conductivity type, an implantation of the second conductivity type on a side opposite the side where the charge storage node is located.
    Advantageously, the pixel structure comprises a front side and a rear side, wherein the photosensitive element and the charge storage element are located at the front side, and the pixel structure further comprises an implantation of the second conductivity type at the rear side.
    Advantageously, another aspect of the invention provides an image sensor composed of a matrix of pixel structures.
    Advantageously, the image sensor is in the form of a rear-exposed image sensor which is intended to be exposed on a side of the image sensor which is away from the charge storage node. The charge storage node can be effectively shielded from light without the use of a light barrier at the rear.
    Advantageously, the image sensor further comprises control logic which is set up to ensure that the matrix of pixel structures is exposed synchronously. Advantageously, the control logic is configured to read a voltage signal from the pixel structures in the matrix for a first exposure period while the pixel structures are exposed for a second exposure period.
    Advantageously, the charge storage node provides in-pixel charge storage and can be used to store one or more signal values for a given period of time. This is useful for global shutter operation. A shielded function of the third region can also provide benefits for a pixel structure where the charge storage element is the charge-to-voltage conversion element (e.g., a floating diffusion, fd). In this type of pixel structure, charge is (briefly) stored on the charge-to-voltage conversion element during a readout. This can provide an advantage that the signal read out from the pixel after exposure time has a reduced sensitivity to light during readout and / or can increase the fill factor of the pixel structure by allowing charge to be generated in the epitaxial layer below the third area, wherein that charge reaches the photosensitive element rather than another, unwanted, part of the pixel structure.
    The pixel matrix can be made in a technology such as Complementary Metal Oxide Semiconductor (CMOS). Another aspect of the invention provides a method of making a pixel structure by creating regions and the epitaxial layer of the pixel structure, and for a method of making image sensors consisting of a matrix of pixel structures.
    The preferred features can be combined as desired, as can be expected from a person skilled in the art, and can be combined with any of the aspects of the invention.
    Brief description of the drawings
    Embodiments of the invention will be described, by way of example only, with reference to the accompanying drawings, wherein:
    Figure 1 shows a pixel fabricated on a p-type epitaxial layer with a 3-phase charge transfer and storage stage for global shutter operation as known in the art;
    Figure 2 shows a pixel fabricated on a p-type epitaxial layer with a 3-phase charge transfer and storage stage which is isolated by p-type implantation under the charge storage stage;
    Figure 3 shows the potential profiles along sections A-A ', B-B' and C-C 'in Figures 1 and 2;
    Figure 4 shows a pixel according to a first embodiment of the present invention, on an n-type epitaxial layer and with p-type isolation implantation under the charge storage node, and with lateral isolation with a deep p implantation;
    Figure 5 shows a second embodiment of the present invention, with lateral isolation of an area extending to the p ++ substrate;
    Figure 6 shows the potential profile along sections C-C 'and D-D' in Figure 4;
    Figure 7 shows another embodiment of the present invention, wherein the p-well isolation implant for the storage node extends only partially below the first transfer port;
    Figure 8 shows another embodiment of the present invention, wherein the p-well isolation implantation of the storage node extends only below the storage port and the final transfer port;
    Figure 9 shows another embodiment of the present invention without deep lateral p isolation implantations;
    Figure 10 shows another embodiment of the present invention without a lateral anti-overexposure transistor;
    Figure 11 shows another embodiment of the present invention, on a global shutter pixel that stores the photo signal directly on the floating diffusion, and wherein the floating diffusion is isolated by a p-well isolation implant;
    Figure 12 shows an embodiment similar to Figure 10, but without a lateral anti-overexposure transistor and with a deep lateral p isolation implant that extends to the p ++ substrate;
    Figure 13 shows a pixel structure similar to Figure 4 but without shallow slot insulation ("shallow trench isolation", STI);
    Fig. 14 shows an embodiment of the present invention used on a diluted rear view image sensor;
    Figure 15 shows another embodiment of the present invention with rear exposure and a different rear passivation technique;
    Figure 16 shows a top view of the layout of the pixel of Figure 4;
    Figure 17 shows a top view of the layout of the pixel of Figure 12;
    Figure 18 shows exposure and readout timing for a pixel;
    Figure 19 shows a pixel structure with storage capacities;
    Fig. 20 shows a pixel structure with a second pinned diode as the charge storage node;
    Figure 21 shows a pixel structure with further an epitaxial layer between the epitaxial layer of the first conductivity type and the substrate of the second conductivity type;
    Figure 22 shows a pixel matrix consisting of one of the pixel structures described in earlier figures.
    Detailed description
    Embodiments of the present invention are described below by way of example only. These examples represent the best ways to practice the invention that are currently known to the applicant, although these are not the only ways in which this can be carried out. The description describes the functions of the examples and the sequence of steps to construct and execute the example. However, the same or similar functions and sequences can be obtained by other examples.
    Figure 4 shows an embodiment of a pixel structure that can form part of a matrix of pixels of an image sensor. The pixel generally has a first flat surface 17 which can be called a front side and a second flat surface 18 which can be called the rear side. In an image sensor which is intended to be exposed from the front side 17, there is usually a substrate 6 at the rear side. In an image sensor which is intended to be exposed from the rear side 18, the substrate 6 is omitted. The pixel structure comprises an epitaxial layer 1 of a first conductivity type. A pinned diode comprises a first region 4 of a second conductivity type adjacent to the front side 17, and a second region 3 of the first conductivity type located between the epitaxial layer 1 and the first region 4. In Fig. 4, the first conductivity type is n-type and the second conductivity type is p-type. Areas 3, 4 can be formed during the manufacture of the image sensor by implantations. A charge storage node 02 is provided to store charge previously collected by the photodiode. In Figure 4, the charge storage node consists of a port 02 and the charge is stored in an inversion layer below the port. The pixel structure further comprises a third region 2 of the second conductivity type positioned between the charge storage element 02 and the epitaxial layer 1. A charge-to-voltage conversion element 13, called a floating diffusion, fd, is provided to convert charge that is received from the charge storage node 02, to a voltage signal. The charge-to-voltage conversion element / floating diffusion fd 13 is a region of the first conductivity type (n +) without the third region 2. An output circuit 21, 22 is provided for selectively bringing the signal from the pixel to the output.
    The charge storage node can be used to store charge collected by the photodiode during an exposure time. In Fig. 4, the charge storage node is the area below 02. During use, charge can be selectively transferred between the photo diode and the charge storage node 02 by using gate 0l. Charge can be selectively transferred between the charge storage node 02 and the floating diffusion (fd) by using port 03. A reset switch is provided to reset the floating diffusion (fd) to a supply potential vdd.
    The pixel structure of Fig. 4 improves the parasitic light sensitivity by (considerably) increasing the potential barrier by using a p-n junction set in barrier. A p-n junction set to block is used as a charge barrier between the active n-type detector layer 1 and the charge storage node 02. The n-type epitaxial layer 1 serves as an active detector layer. This is the layer in which the photo charge is generated. Figure 6 shows the potential profile along a vertical section C-C '(through the pinned photodiode) and D-D' (through the charge storage port). The cross-section C-C 'is similar to the cross-section previously shown in Figure 3. The potential is at its highest in the pinned photodiode. The section D-D 'shows a potential barrier between the active n-epi detector layer 1 and the charge storage node formed by the p-well / n-epi junction set in reverse. The potential along this barrier is considerably higher than in the case of Figure 2. For an abrupt n / p junction, the potential barrier can be calculated as:
    where k = Boltzmann's constant, T = absolute temperature, q = elemental charge, Na and Nd are the concentrations of the acceptor and donor impurities in the p + and n + regions respectively, and m is the intrinsic charge density of silicon. For typical values of Nd = 5E17 / cm3 (p +) and Afo = 5E14 / cm3, and an intrinsic charge density m of 1.2E10 / cm3 at 300K, this built-in potential barrier is 1.2V, which is considerably higher than the 134 mV that is obtained by the p-well / p-homojunction in Figure 2. This potential barrier serves, during use, to shield the charge storage node from the active detector layer 1.
    The surface p + region 4 is used to form a depletion region in the n-type photodiode 3 which completely depletes the diode. At the bottom, the p ++ bulk substrate 6 is used to deplete the n-epitaxial layer 1. The depletion area of the top and bottom touch each other and the structure is completely depleted. A third depletion region is formed by the p-well 2 / n-epi layer 1 junction. It also depletes the part of the n-epitaxial layer 1 below the p-well 2. The potential in the n-epi region below the p-well 2 will be lower than in the n-region below the photodiode, which leads the electrons to the photodiode.
    The n-epitaxial region 1 forms a junction with the p region 2 above the n-epitaxial layer. It also forms a junction with the p ++ bulk wafer 6, if present. Both junctions form a depletion area. Preferably, but not essential, the n-epitaxial region 1 below the p-well region 2 is completely depleted. When the photodiode collects more electrons, the voltage on the photodiode drops. At some point, the voltage on the photodiode is low enough so that additional charge will also flow into the n-epitaxial region 1 below the p-well 2. Without any measures, the charge can then run freely to the neighboring pixels. This is preferably avoided. This can be avoided by providing a deep p-type isolation implant 5 at the edge of the pixel. This isolation implant 5 forms a potential barrier which prevents lateral diffusion of photoelectrons to neighboring pixels. The p-type isolation implant 5 may be connected to the p + region in the substrate, as shown in Figure 5, or it must not be physically connected, as shown in Figure 4. If it is not physically connected, it will still be a isolation due to the complete depletion of the n region 1 below the p implantation region 5, which remains depleted at a lower potential than in the rest of the pixel.
    An additional advantage of the pixel structure is that it is easier for charges generated in the p-well region 2 to diffuse away from this region and diffuse to the photodiode. With the structure shown in Figure 2, this path is much less likely because of the much weaker electric field in that direction.
    It is possible to provide a light screen 11 above the storage port 02, as shown in figure 5. Alternatively, this light screen 11 can be omitted, as shown in figure 4. An advantage of omitting the light screen 11 is that more photo charges are generated in the pixel and that, as described above, even charges generated in the p-well region can contribute to the charge integrated on the photodiode.
    Global shutter pixels with in-pixel charge domain storage of the photo signal on a storage node require a low sensitivity of the storage node to light. This parameter is measured quantitatively as the parasitic light sensitivity or shutter efficiency. The parasitic light sensitivity of the storage node indicates the sensitivity of the storage node to light. If an image is exposed during an exposure time TeXp, and then stored during a storage time Tstore on an in-pixel storage node, with a constant light level, then for an ideal global shutter pixel, the output signal of the pixel will be proportional to Texp and invariable when Tstore is increased. In reality, the pixel's output signal will also be sensitive to the storage time Tstore. The SPiX output signal measured at the pixel output under a constant light level is given by the following equation
    wherein parameters a and b are proportional to the light level and the light sensitivity of the photodiode and the storage node, respectively. The ratio b / a between the two factors is called the parasitic light sensitivity (PLS). Sometimes this property is characterized by the shutter efficiency given by the comparison:
    When the pixel is fully saturated, the potential well is created by the junction profiles completely filled with electrons. The remaining electrons must be removed. There are different possible directions in which these electrons can flow. It is not desirable that these electrons reach the charge storage node 02. It is also undesirable that these charges overflow to neighboring pixels because that causes a 'blooming' effect in overexposure. This effect is visible as a rapid and large increase in white spots with strongly overexposed pixels. Preferably, some anti-blooming measures have been taken in the pixel. Figures 4 and 5 show a lateral anti-blooming transistor AB. The drain of the anti-bloom transistor is connected to a constant DC voltage Vab, typically equal to Vdd. The gate of the anti-blooming transistor is connected to a low DC potential. This potential is typically higher than the potential applied to 0l during the exposure time, to prevent charges from flowing into the storage port O2. Instead of different gate voltages, this can also be realized by different threshold voltages for the ab gate and the 0l gate. When the photodiode is filled with electrons, the excess electrons are carried away by this anti-blooming transistor to the Vab drain, which is typically the power supply. The anti-blooming transistor consumes surface area of the pixel and it may be desirable to avoid using such a transistor. There are other possible drain paths for electrons in a saturated photodiode. First, the load can run vertically to the p ++ bulk wafer 6. Alternatively, the load can be drained laterally into the p-type isolation implants 5. Both load drains are only possible if it is ensured that the load does not run below port 01. This can be achieved by placing 0I at a low potential, which may be negative such as -IV. When the gate is strongly negative, the gate can be operated in accumulation, whereby an accumulation layer of holes is formed under the gate. This has an additional advantage that the dark current contribution under this gate is avoided. Electrons generated on the silicon surface below this gate will immediately recombine when holes have accumulated under this gate. Instead of a negative voltage, it is also possible to increase the threshold voltage of the transfer port by the doping type of the port material (e.g., p-type port). A pixel structure without an anti-blooming transistor is shown in Figure 10.
    In Figures 4 and 5, the p-well region 2 is present below the charge storage node 02 and the p-well region extends to the photodiode regions 3, 4. In alternative embodiments, this p-well region 2 can only extend below the charge storage node 02. The extent to which the p-well region 2 extends can depend on the characteristics of the transfer port 0l. When the p-well extends completely below the transfer port 11 to the photodiode, the side of the photo diode can remain permanently depleted even when the port 11 is turned on (at a high potential). This can completely or partially block the load transfer. Figure 7 shows a p-well region 2 partially extending below port 11. Figure 8 shows a p-well region 2 that does not extend below gate 11, but is only present under storage port 02 and transfer port 03. The p-well region 2 is also present under the floating diffusion (fd) to isolate this n + junction of the n-epi. A p-well of the same, or different, concentration as region 2 can also be present under the reset transistor, the source follower 21, and the selection transistor 22 of the pixel.
    Figures 11 and 12 show how this isolation technique can be used for 5-transistor (5T) pixels. These pixels can be used in a rolling shutter mode or in a global shutter mode. In both modes, the charge-to-voltage conversion element also serves as a charge storage node. First, global shutter operation will be described. The n + floating diffusion implant 13 is used to store charge in global shutter operation. Charge is synchronously transferred in all pixels of the pixel matrix from the pinned diode to the floating diffusion fd 13 at the end of the exposure time. The signals are then sampled on the floating diffusion fd 13 sequentially read, row-by-row. The signals remain sampled on the floating diffusion 13 until the pixel is read. Second, rolling shutter operation is described. At the end of the exposure time, charges are transferred from the pinned photodiode to the floating diffusion fd 13. Then the signal is sampled on the floating diffusion 13 read out. Pixels are read on a row-by-row basis. The time period during which signals are sampled on the floating diffusion 13 is minimal. During exposure, charges generated under the p-well 2 are immediately discharged to the photodiode, rather than being collected by unrelated n + junctions in the pixel. Charges generated in the p-well 2 can escape to the n-epi region and contribute to the photo signal, rather than being caught by an unrelated n + junction.
    The floating diffusion / charge storage node fd must be shielded from parasitic light and from photo charges that diffuse into the substrate. Embodiments of the invention provide better shielding of the storage node for parasitic light. The anti-blooming transistor, shown in Fig. 11, is again optional, and can be replaced with a vertical or lateral anti-blooming by discharging excess charges to the p + bulk wafer or the p isolation regions 5. In that case, a simpler 4-transistor pixel configuration, as shown in figure 12. Another difference between figures 11 and 12 is the extension of the p-well below the transfer port 0l. In Fig. 11, the p-well extends fully to the pinned photodiode, while in Fig. 12 it extends only partially below gate 11. The best configuration depends on the charge transfer characteristic of 0l, which in turn depends on the implantation concentrations and the electric fields in the structure.
    In Figures 4, 5, 7-12, the n + and p + implantation regions are isolated by thin slot insulation, "Shallow Trench Isolation" or STI. Slots 15 filled with oxide or another dielectric are used to isolate the different junctions within and between pixels. Instead of STI, this isolation can also be performed by the p-well implants and p + surface layers as shown in Figure 13. The n + layers are separated within the p-well regions. The p-well is connected to p + areas on the ground. The depletion region around each n + diffusion extends into the p-well, but the distance between neighboring n + regions is sufficiently large to provide good insulation between these regions. A typical width is comparable to the minimum gate length of the transistors that can be made in the technology used. This makes it possible to create a more planar structure, which reduces the dark current and the distribution of dark current between different pixels. It can also reduce the number of white pixels. The boron p + regions used for isolation can act as effective collection centers to collect foreign contaminants in the epitaxial layer, such as certain metal ions. Some metal ions are preferred to be collected by drill implants.
    Embodiments can be applied to rear-exposed image sensors. A rear-exposed image sensor is exposed on a side opposite the side of the image sensor where the gates are formed. Fig. 14 shows a rear-exposed image sensor, with ports formed on the top of the image sensor. The image sensor is exposed on the bottom. The p ++ substrate layer 6 is not present and has been replaced by a thin p ++ implantation 7. This p ++ implantation layer 7 can be realized, for example, by a shallow implantation that is activated by a laser activation step, as known. The p + layer 7 creates a backside ground potential and passivates the backside. An anti-reflective coating 9 can be applied on top of this rear silicon layer to improve the light coupling in the silicon. Figure 15 shows an alternative embodiment with a layer 8 with fixed negative charges, such as Al 2 O 3 (Aluminum Oxide) or a thin layer of HfO (Hafnium Oxide). Such a layer will attract holes that form a hole accumulation layer at the rear. This layer also effectively passivates the back and creates an electric field in the right direction for the electrons. This passivation technique is further described in US patent US 8,283,195. The form of isolation on the storage node against electrons diffusing in the epitaxial layer, as described in this invention, allows to create global shutter pixels with rear exposure and good shutter efficiency. This is not possible in a back-lit pixel when no isolation technique is used, or when a light shield is used to shield the storage nodes, or when a simple difference in concentration of dopant with the same conductivity type is used.
    Placing a light screen at the rear of a rear-exposed image sensor is a complex additional process step, which also reduces the fill factor and light sensitivity of the pixel. Also, most photoelectrons are generated close to the silicon back surface and have to diffuse to the photodiode. Diffusion to the storage node is more likely in the case of a rear-exposed image sensor. In embodiments of the invention, the charge storage node is effectively shielded from photo charges and light without using a light screen.
    Figure 16 shows a top view of a mask layout of a pixel structure of the type shown in Figures 4-10 and 13-15. The STI mask is shown in continuous lines. STI is present everywhere except on the pinned photodiode and the transistors (also called the 'active area' of the structure.) Different implantations are aligned on the STI. The polysilicon ports 0l, 02, 03, RST and ab are also shown. n + implantation masks align on the polysilicon ports and on the STI and implant the floating diffusion and the vdd contacts.The pinned diode is formed by a p + surface implantation and a deeper n implantation that may or may not be aligned with the STI and / or the polysilicon The p-well mask defines the area of the pixel with the p-well implant The p-well must be present at least under the storage node (02 in this case). It is also typically required under the transistor ports of the pixel (reset port, source follower, selection transistor) It may or may not be partially present under the first transfer port and the anti-blooming port The deeper p-isolation implantation is defined by a band long sheen the edge of the pixel, and forms an effective isolation between neighboring pixels.
    Figure 17 shows a top view of a pixel structure of the type shown in Figures 11 and 12. Similar masks are used as in Figure 16. The floating diffusion is placed in the p-well, since this node is used to store charge after exposure.
    Figure 18 shows two pixel structures: a first pixel structure with a photo gate as a photosensitive element, instead of a pinned photo diode; and a second pixel structure which is the same as previously shown in Figure 7. A timing diagram for the operation of the pixel structures is also shown. Vab is pulsed to an intermediate level during exposure, sufficiently higher than the low area at 0l, but still low enough to keep charge stored on the photo gate or photodiode. During the readout, Vab can be pulsed to a low level as shown in the timing diagram. Alternatively, Vab can remain at a fixed potential, higher than the low level of 01. The photo gate signal is only used in the case of the photo gate as a charge collecting element. It is not used in the case of a pinned photo diode.
    Figure 19 shows a pixel structure that is capable of operating with a global shutter. It can store a signal value on any of capacities C1 and C2. During use, the pixel can store a reset value on C2 and a signal value on C1. A pixel structure of this type is described in EP 2 109 306. A port instead of a capacity can be used to store a signal value. The port or capacitance itself does not collect charges, but there is a switch associated with this capacitance, such as the switches S1 and S2 shown in Figure 19. Such a switch includes small n + source / drain surfaces that can still collect charge. In embodiments of the invention, these n + junctions are shielded from parasitic charges that diffuse into the epitaxial layer, in the same way as a charge storage node is shielded in the previously described pixels. The potential difference between the p-well and the underlying n-epitaxial layer ensures that electrons will diffuse into the n-epitaxial layer and that electrons in the n-epitaxial layer will not diffuse up to the p-well and further to the n + junctions of switches S1 and S2. This further improves the parasitic light sensitivity for this pixel with internal capacities. This principle can also be applied to other topologies described in more detail in EP 2 109 306, such as pixels that use a single in-pixel storage capacity, or two capacities in parallel.
    In these embodiments, there is a charge storage element consisting of the capacity C1 (or C2) and the parasitic capacity connected to this node. The capacitor C1 or C2 is a metal-metal capacitance or the gate-to-channel capacitance of a transistor. In the latter case, the channel is connected to the ground. The port itself is unable to collect photo charges, so the capacity itself is not light sensitive. The parasitic capacities include metal routing (interconnections that do not collect charge) and junctions of switches connected to the capacitances. These junctions are the n + source / drain regions of switch S2 and the n + drain of switch S1 in Figure 19. These junctions are capable of collecting electrons from the underlying substrate and benefiting from shielding, although these junctions are not the main place where the charge of an exposure is stored, they form part of a current path to a charge storage element and are capable of storing charge These junctions can be considered as charge storage nodes that are part of a charge storage element.
    Figure 20 shows a pinned diode 19 used as a charge storage element. The pinned diode is positioned between a transfer port 0l and a transfer port 03. The pinned diode is completely depleted at a higher potential than the pinned diode formed by regions 3 and 4. When 0l is turned on, all charge will run from the pinned diode to the pinned diode 19 due to the potential difference between the two photodiodes. The pinned diode 19 must also be protected against charges that diffuse into the epitaxial layer. Again, the p-well / n-epi forms a barrier against such charge diffusion.
    For each of the embodiments described above, doping levels may be, for example: region 1: epitaxial layer n-type 5E14 / cm 3 or lower; area 2: p-well. around lE17 / cm3 - lE18 / cm3. Significantly higher than the n-type area, but lower than the n + surface implantations that form the transistor source / drain junctions (the n + surface MOSFET source / drain implantations). Area 3: photodiode n-layer. Between 5E16 / cm3 and lE18 / cm3; area 4: photodiode area p + low Significantly higher than area 3, lE18 / cm3 to 5E19 / cm3; area 5: p insulation layer Similar to the p-well, around l17 / cm3 to lE18 / cm3. area 6: p ++ substrate (if present): highly doped, similar to area 4 or higher p-well surface contact (p +, Figures 11, 12): around 5E19 / cm3, similar to the p + MOSFET source / drain surface implantations.
    A matrix of pixel structures as described above can be operated with a rolling shutter function, or a global shutter function. For a global shutter function, there is a requirement to store a signal in a pixel for a longer period of time, and therefore a greater need for a lower sensitivity of the storage node to light. Control logic is designed so that the matrix of pixel structures is exposed synchronously. The control logic is also designed to read a voltage signal from the pixel structures in the matrix for a first exposure period while the pixel structures are exposed for a second exposure period. Alternatively, all pixels can be read out before the next exposure period is started in the pixels. A signal, or two signals [signal and reset] can be read from each pixel during the readout.
    Pixel structures as described above can work with noise-free storage if the photo charges are transferred to the storage node, and remain in the charge domain. These pixel structures can be implemented by a small 3-phase in-pixel charge-coupled structure, as described in S. Lauxterman, & co., "Comparison of Global Shutter Pixels for CMOS Image Sensors", proc. International Image Sensor Workshop 2007, Ogunquit, ME, June 6-10, 2007 (available at www.imagesensors.org) and in US 7,271,835. This publication shows a sequence of 3 transfer ports linked to a pinned photo diode. The middle transfer port is used as a storage node to store cargo and is called the storage port. After exposure, the charges are transferred from the pinned photodiode to the middle storage node via a first transfer port connected between the two. To read out the pixel, the floating diffusion is first reset, and this reset level is sampled by the readout circuit (in the column amplifier or in the output amplifier). The load is then transferred from the storage port through the third transfer port to the load conversion node. The voltage on the charge conversion node changes and the new voltage is resampled. The difference between the two sampled values is a measure of the photo charge, and free of kTC reset noise from the charge conversion node (fd).
    An alternative form of the storage node is a pinned diode, as shown in Fig. 20. A pixel structure of this type is described in H-J. Yoon & Co., "A CMOS Image Sensor With In-Pixel Two-Stage Charge Transfer for Fluorescence Lifetime Imaging", IEEE trans. El. Dev, Vol. 56, No.2, Feb. 2009. The storage node is a pinned photodiode which is now at a fixed potential when the diode is depleted. This fixed potential is higher than the potential of the diode when it is depleted. The transfer port between the pinned photo diode and the storage node transfers the charge packets synchronously to the storage node in all pixels after the exposure period. The transfer port between the storage node and the floating diffusion moves the load to the load conversion node for reading, with the same CDS scheme as quoted in the documents above. The structure with two transfer ports and a pinned storage node can be considered as a 3-phase CCD with a virtual phase in the middle.
    Figure 21 shows a structure similar to Figure 4, but where the p-type substrate consists of two layers: a thick p ++ substrate layer 6 and a p-type epitaxial layer 20. An advantage of the structure of Figure 21 is a better junction quality of the buried p / n junction with fewer recombination losses. The p-type epitaxial layer 20 keeps the buried p / n junction away from the p ++ substrate 6. This p ++ substrate is typically formed by Czochralski (CZ) growth, which may be of lesser quality than the p-type layer 20 that is formed by epitaxial growth. The concentration of the p-type epitaxial layer 20 is sufficiently high to deplete the n-type epitaxial layer 1 from the bottom. The use of an epitaxial layer 20 of the second conductivity type (p-type) can be applied to any of the embodiments where a substrate 6 is available.
    Fig. 22 shows an image sensor consisting of a matrix of pixel structures 10 of any of the types described above. Control logic 50 controls the operation of the pixel matrix and the output stages 56, 57. Control logic 50 includes logic 51 for controlling the exposure of the pixels 10 and logic 52 for controlling the readout of the pixels. Exposure control logic 51 may include line driving circuits to generate control signals on control lines 53. Readout control logic 52 may include row selection and line driving circuits to generate control signals on control lines 53 to control the reading of pixels 10. Control logic 50 can control the following: resetting the pixels to control the start of an exposure period (including the operation of the transfer ports and the reset switch via control signal RST); operation of the transfer ports to transfer charge to the charge storage nodes and / or the floating diffusion fd; operation of switch 22 by a control signal SEL to control the reading of a pixel.
    Examples of timing diagrams for the control signals are shown, and are known to those skilled in the art. The pixel matrix can be read in a conventional manner, with pixels scanned on a row-by-row basis. Alternatively, control logic 50 can perform a global shutter function by synchronous operation of the control signals which control the respective exposure of each of the pixels in the pixel matrix. The control logic 50 can be stored in hard-coded form, such as in an application-specific integrated circuit, or it can be stored in a form of reconfigurable processing device, such as a logical matrix (programmable array, reconfiguarble array] or a general processor that controls software All elements shown in Fig. 21 can be provided on a single semiconductor chip, or the elements can be divided among several separate chips Column output stage 56 can include column processing circuits specific to each column, such as, an analog-to-digital converter (ADC), one or multiple amplifiers, storage to store signal values for the purpose of performing functions such as correlated double sampling (CDS) An output stage 57 may perform further processing of the signals received from the columns in the matrix.
    Embodiments can also be applied to pixels that use multiple storage nodes to store signals from multiple exposures in a pixel. These pixels record a sequence of n images, which are sequentially stored in n memory elements in the pixel. Each of these memory elements is composed of structures as described in this text, such as capacities, storage ports, or floating diffusions. After the sequence of images has been recorded, the n memory elements are read out. In this case, too, it is essential that the memory elements are shielded from light or photo charges.
    Embodiments shown in the drawings and described above have the first conductivity type as n-type and the second conductivity type as p-type. It is also possible to use the p-type as the first conductivity type and the n-type as the second conductivity type. The pixel structure will consist of a p-type epitaxial layer 1, an n-well implant 2 to shield the charge storage node and a pinned diode consisting of a deep p implantation [area 3] with an area n + / n ++ implantation [area 4 ).
    Although the photosensitive element (pinned diode) shown in the embodiments is connected to a single transfer port, two or more transfer ports can be connected to the photosensitive element, as shown in EP 2 346 079 A1 and US2012 / 002089A1. Each of the charge storage nodes and / or charge conversion elements can be shielded in the manner described above.
    Any range or value described herein can be expanded or changed without losing the intended effect, as will be apparent to those skilled in the art.
    It will be understood that the advantages described above may be related to an embodiment or multiple embodiments. The embodiments are not limited to those that solve one or all of the stated problems or to those that have one or all of the stated advantages.
    Each reference to an item refers to one or more of these items. The term "comprising" is used herein to mean that the identified blocks or elements are included, but does not mean that these blocks or elements form an exclusive list, and a method or device may include additional blocks or elements.
    The steps of the methods described herein may be performed in any suitable order, or simultaneously if appropriate. In addition, individual blocks can be omitted from any of the methods without departing from the spirit and purpose of the subject matter described herein. Aspects of any of the examples described herein can be combined with aspects of any of the other examples described to form further examples without losing the intended effect.
    It will be understood that the above description of a preferred embodiment is given by way of example only and that a person skilled in the art can make various changes. Although various embodiments have been described above with a certain form of specificity, or with reference to one or more individual embodiments, those skilled in the art can make all kinds of changes to the described forms of expression without departing from the invention.
    权利要求:
    Claims (15)
    [1]
    Conclusions
    A pixel structure comprising: an epitaxial layer (1) of a first conductivity type; a photosensitive element comprising a first region (4) of a second conductivity type and a second region (3) of the first conductivity type, positioned between the epitaxial layer [1) and the first region (4); a charge storage node (02) designed to store charge collected by the photosensitive element, or to form part of a charge storage element; a third region of the second conductivity type, positioned between the charge storage element and the epitaxial layer; a charge-to-voltage conversion element (13) for converting charge from the charge storage node (02) to a voltage signal; and, an output circuit (21, 22) for selectively outputting a voltage signal from the pixel structure.
    [2]
    The pixel structure of claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.
    [3]
    The pixel structure according to claims 1 or 2, wherein a doping level of the third region (2) is higher than the doping level of the epitaxial layer (1).
    [4]
    The pixel structure according to any of the preceding claims, wherein a doping level of the second region (3) is higher than the doping level of the epitaxial layer (1).
    [5]
    A pixel structure according to any of the preceding claims, wherein the charge storage node (02) consists of one of: a floating diffusion, a transfer port, a capacitance plate, a pinned diode.
    [6]
    The pixel structure according to any of the preceding claims, wherein the charge-to-voltage conversion element (13) is an area of the first conductivity type in the third area (2).
    [7]
    The pixel structure according to any of the preceding claims, wherein the charge storage node (02) and the charge-to-voltage conversion element (13) are an area of the first conductivity type within the third area (2).
    [8]
    The pixel structure according to any of the preceding claims, wherein the charge storage node (02) is positioned between a photosensitive element and the charge-to-voltage conversion element (13).
    [9]
    The pixel structure of claim 8, further comprising at least one of: a transfer port (0l) positioned between the charge sensitive element and a charge storage node; a transfer port (03) positioned between the charge storage node and the charge-to-voltage conversion element.
    [10]
    The pixel structure according to any of claims 1 to 7, wherein the charge storage node is positioned between the charge-to-voltage conversion element and the output circuit.
    [11]
    A pixel structure according to any of claims 1 to 7, wherein the charge storage node is the charge-to-voltage conversion element.
    [12]
    A pixel structure according to any one of the preceding claims, wherein the third area extends to the first area and the second area of the photosensitive element.
    [13]
    A pixel structure according to any one of the preceding claims, further comprising insulating layers (5) of the second conductivity type adjacent a boundary of the pixel structure to prevent lateral diffusion, the insulating layers being located in the epitaxial layer (1).
    [14]
    The pixel structure of claim 13, wherein the isolation regions (5) extend between the third region (2) and a bottom side of the epitaxial layer (1).
    [15]
    An image sensor, comprising a matrix of pixel structures according to any one of the preceding claims.
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    公开号 | 公开日
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20070109437A1|2005-11-15|2007-05-17|Victor Company Of Japan, Ltd., A Corporation Of Japan|Solid state image sensing device|
    US20090256176A1|2008-04-09|2009-10-15|Canon Kabushiki Kaisha|Solid-state imaging apparatus|
    US20110084316A1|2009-10-09|2011-04-14|Canon Kabushiki Kaisha|Pickup device and method for manufacturing the same|
    EP0883187A1|1997-06-04|1998-12-09|Interuniversitair Micro-Elektronica Centrum Vzw|A detector for electromagnetic radiation, pixel structure with high sensitivity using such detector and method of manufacturing such detector|
    US20090224351A1|2002-08-27|2009-09-10|E-Phocus, Inc|CMOS sensor with approximately equal potential photodiodes|
    JP4403687B2|2002-09-18|2010-01-27|ソニー株式会社|Solid-state imaging device and drive control method thereof|
    US7153719B2|2004-08-24|2006-12-26|Micron Technology, Inc.|Method of fabricating a storage gate pixel design|
    JP4643249B2|2004-12-22|2011-03-02|株式会社東芝|Solid-state imaging device|
    US7928591B2|2005-02-11|2011-04-19|Wintec Industries, Inc.|Apparatus and method for predetermined component placement to a target platform|
    US20070045668A1|2005-08-26|2007-03-01|Micron Technology, Inc.|Vertical anti-blooming control and cross-talk reduction for imagers|
    US7605440B2|2006-04-07|2009-10-20|Aptina Imaging Corporation|Pixel cell isolation of charge storage and floating diffusion regions using doped wells|
    GB0725245D0|2007-12-28|2008-02-06|Cmosis Nv|Semiconductor detector for electromagnetic or particle radiation|
    EP2587794A3|2008-04-07|2014-01-01|Cmosis NV|Pixel array with global shutter|
    US7915652B2|2008-10-24|2011-03-29|Sharp Laboratories Of America, Inc.|Integrated infrared and color CMOS imager sensor|
    JP4752926B2|2009-02-05|2011-08-17|ソニー株式会社|Solid-state imaging device, manufacturing method of solid-state imaging device, driving method of solid-state imaging device, electronic apparatus|
    JP5369779B2|2009-03-12|2013-12-18|ソニー株式会社|Solid-state imaging device, driving method of solid-state imaging device, and electronic apparatus|
    JP5402349B2|2009-07-23|2014-01-29|ソニー株式会社|Solid-state imaging device, driving method thereof, and electronic apparatus|
    GB2475086B|2009-11-05|2014-02-05|Cmosis Nv|Backside illuminated image sensor|
    GB2477083A|2010-01-13|2011-07-27|Cmosis Nv|Pixel structure with multiple transfer gates to improve dynamic range|
    JP2012079979A|2010-10-04|2012-04-19|Sony Corp|Solid-state imaging device, method for manufacturing the same, and electronic apparatus|
    JP5673063B2|2010-12-15|2015-02-18|ソニー株式会社|Solid-state imaging device, driving method, and electronic apparatus|
    US8878264B2|2011-04-26|2014-11-04|Aptina Imaging Corporation|Global shutter pixel with improved efficiency|
    US8575531B2|2011-04-26|2013-11-05|Aptina Imaging Corporation|Image sensor array for back side illumination with global shutter using a junction gate photodiode|US9231020B2|2014-01-16|2016-01-05|Tower Semiconductor Ltd.|Device and method of gettering on silicon on insulatorsubstrate|
    CN104218073A|2014-09-22|2014-12-17|北京思比科微电子技术股份有限公司|Image sensor picture element high in signal swing amplitude and operation method thereof|
    JP6399301B2|2014-11-25|2018-10-03|セイコーエプソン株式会社|Solid-state imaging device and manufacturing method thereof|
    KR102363433B1|2015-01-15|2022-02-16|삼성전자주식회사|Image sensors|
    US10236400B2|2016-02-01|2019-03-19|Heptagon Micro Optics Pte. Ltd.|Quantum dot film based demodulation structures|
    US10469775B2|2017-03-31|2019-11-05|Semiconductor Components Industries, Llc|High dynamic range storage gate pixel circuitry|
    EP3474038A1|2017-10-23|2019-04-24|ams International AG|Image sensor for determining a three-dimensional image and method for determining a three-dimensional image|
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    GB13026646|2013-02-15|
    GBGB1302664.6A|GB201302664D0|2013-02-15|2013-02-15|A pixel structure|
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